UPD78F1502AGK-GAK-AX Datasheet, PDF (1000/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(28/39)
Page
DMA
controller
Priority
Response time
During DMA transfer, a request from the other DMA channel is held pending even if p.738 _†
generated. The pending DMA transfer is started after the ongoing DMA transfer is
completed. If two DMA requests are generated at the same time, however, DMA
channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA
transfer takes precedence, and then interrupt servicing is executed.
The response time of DMA transfer is as follows. (See Table 18-2.)
p.738 _†
Interrupt
functions
Operation in
The DMA controller operates as follows in the standby mode. (See Table 18-3.) p.739 _†
standby mode
DMA pending Even if a DMA request is generated, DMA transfer is held pending immediately after p.739 _†
instruction
the following instructions.
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L,
MK0H, MK1L, MK1H, MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L,
PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H and PSW each.
Operation if
The address indicated by DRA0n is incremented during DMA transfer. If the address p.739 _†
address in
is incremented to an address in the general-purpose register area or exceeds the
general-purpose area of the internal RAM, the following operation is performed.
register area or z In mode of transfer from SFR to RAM
other than those The data of that address is lost.
of internal RAM z In mode of transfer from RAM to SFR
area is specified Undefined data is transferred to SFR.
In either case, malfunctioning may occur or damage may be done to the system.
Therefore, make sure that the address is within the internal RAM area other than the
general-purpose register area.
IF0L, IF0H, IF1L, When operating a timer, serial interface, or A/D converter after standby release, p.748 _†
IF1H, IF2L, IF2H: operate it once after clearing the interrupt request flag. An interrupt request flag may
Interrupt request be set by noise.
flag registers
R01UH0004EJ0501 Rev.5.01
984
Jun 20, 2011