UPD78F1502AGK-GAK-AX Datasheet, PDF (567/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(3) Permissible baud rate range for reception
The permissible baud rate range for reception during UART (UART0, UART1, UART2, UART3) communication can
be calculated by the following expression. Make sure that the baud rate at the transmission side is within the
permissible baud rate range at the reception side.
(Maximum receivable baud rate) =
2 × k × Nfr
2 × k × Nfr − k + 2
× Brate
(Minimum receivable baud rate) =
2 × k × (Nfr − 1)
2 × k × Nfr − k − 2
× Brate
Brate: Calculated baud rate value at the reception side (See 14.6.5 (1) Baud rate calculation expression.)
k: SDRmn[15:9] + 1
Nfr: 1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
Figure 14-87. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
Latch
timing
Data frame length
of SAU
Start
bit
Bit 0
FL
Bit 1
Bit 7
Parity
bit
Stop
bit
1 data frame (11 × FL)
Permissible minimum
data frame length
Start
bit
Bit 0
Bit 1
Bit 7
(11 × FL) min.
Parity
bit
Stop
bit
Permissible maximum
data frame length
Start
bit
Bit 0
Bit 1
Bit 7
(11 × FL) max.
Parity
bit
Stop
bit
As shown in Figure 14-87, the timing of latching receive data is determined by the division ratio set by bits 15 to 9
of the serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this
latch timing, the data can be correctly received.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011