UPD78F1502AGK-GAK-AX Datasheet, PDF (816/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) When LVI is OFF upon power application (option byte: LVIOFF = 1)
Supply voltage
(VDD)
VLVI
1.8 V^{Note 1}
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
0V
Internal high-speed
oscillation clock (fIH)
High-speed
system clock (fMX)
(when X1 oscillation
is selected)
Operation
CPU _stops
Internal reset signal
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Set LVI to be
used for reset
0.5 V/ms (MIN.)^{Note 2}
Wait for oscillation
accuracy stabilization^{Note 3}
Wait for oscillation
accuracy stabilization^{Note 4}
Wait for oscillation
accuracy stabilization^{Note 3}
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Reset processing
(about 2.1 to 5.8 ms)
Normal operation
Reset
period
(internal high-speed _(oscillation
oscillation clock)^{Note 5} stop)
Normal operation
(internal high-speed
oscillation clock)^{Note 5}
Reset Reset processing
period _{(about 2.1 to 5.8 ms)}
(oscillation
stop)
Reset processing (about 195 to 322 ms)
Normal operation
(internal high-speed
oscillation clock)^{Note 5}
Operation stops
Notes 1.
2.
3.
4.
5.
The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset state
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.), input a
low level to the RESET pin before the voltage reaches to 1.8 V, or set LVI to ON by default by using an
option byte (option byte: LVIOFF = 0).
The reset processing time, such as when waiting for internal voltage stabilization, includes the oscillation
accuracy stabilization time of the internal high-speed oscillation clock.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-
speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of
the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24 LOW-
VOLTAGE DETECTOR).
Remark
VLVI: LVI detection voltage
VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
R01UH0004EJ0501 Rev.5.01
800
Jun 20, 2011