UPD78F1502AGK-GAK-AX Datasheet, PDF (605/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
(3) IICA status register (IICS)
This register indicates the status of I²C.
IICS is read by a 1-bit or 8-bit memory manipulation instruction only when STT = 1 and during the wait period.
Reset signal generation clears this register to 00H.
Caution
Reading the IICS register while the address match wakeup function is enabled (WUP = 1) in STOP
mode is prohibited. When the WUP bit is changed from 1 to 0 (wakeup operation is stopped),
regardless of the INTIICA interrupt request, the change in status is not reflected until the next
start condition or stop condition is detected. To use the wakeup function, therefore, enable (SPIE
= 1) the interrupt generated by detecting a stop condition and read the IICS register after the
interrupt has been detected.
Remark STT: bit 1 of IICA control register 0 (IICCTL0)
WUP: bit 7 of IICA control register 1 (IICCTL1)
Figure 15-7. Format of IICA Status Register (IICS) (1/3)
Address: FFF51H
After reset: 00H R
Symbol
<7>
<6>
<5>
<4>
IICS
MSTS
ALD
EXC
COI
<3>
TRC
<2>
ACKD
<1>
STD
<0>
SPD
MSTS
Master status check flag
0
Slave device status or communication standby status
1
Master device communication status
Condition for clearing (MSTS = 0)
Condition for setting (MSTS = 1)
• When a stop condition is detected
• When ALD = 1 (arbitration loss)
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
• When a start condition is generated
ALD
Detection of arbitration loss
0
This status means either that there was no arbitration or that the arbitration result was a “win”.
1
This status indicates the arbitration result was a “loss”. MSTS is cleared.
Condition for clearing (ALD = 0)
• Automatically cleared after IICS is read^Note
• When IICE changes from 1 to 0 (operation stop)
• Reset
Condition for setting (ALD = 1)
• When the arbitration result is a “loss”.
EXC
Detection of extension code reception
0
Extension code was not received.
1
Extension code was received.
Condition for clearing (EXC = 0)
Condition for setting (EXC = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE changes from 1 to 0 (operation stop)
• Reset
• When the higher four bits of the received address
data is either “0000” or “1111” (set at the rising edge
of the eighth clock).
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than
IICS. Therefore, when using the ALD bit, read the data of this bit before the data of the other bits.
Remark LREL: Bit 6 of IICA control register 0 (IICCTL0)
IICE: Bit 7 of IICA control register 0 (IICCTL0)
R01UH0004EJ0501 Rev.5.01
589
Jun 20, 2011