UPD78F1502AGK-GAK-AX Datasheet, PDF (975/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(3/39)
Page
Pin
functions
Memory
space
P110/ANO0,
When using at least one port of P110/ANO0 and P111/ANO1 as a digital port, set p.54 _†
P111/ANO1
P121 to P124
AVDD1 to the same potential as EVDD or VDD.
The function setting on P121 to P124 is available only once after the reset release. p.55 _†
The port once set for connection to an oscillator cannot be used as an input port
unless the reset is performed.
P150/ANI8/
P150/ANI8/AMP2+ to P152/ANI10 and P157/ANI15/AVREFM are set in the digital input p.57 _†
AMP2+ to
(general-purpose port) mode after release of reset.
P152/ANI10 and When using at least one port of P150/ANI8/AMP2+ to P152/ANI10 and p.57 _†
P157/ANI15/
P157/ANI15/AVREFM as a digital port, set AVDD0 to the same potential as EVDD or VDD.
AVREFM
REGC
Keep the wiring length as short as possible for the broken-line part in the above p.58 _†
figure.
PMC: Processor Set PMC only once during the initial settings prior to operating the DMA controller. p.83 _†
mode control Rewriting PMC other than during the initial settings is prohibited.
register
After setting PMC, wait for at least one instruction and access the mirror area.
p.83 _†
When the μPD78F1500A, 78F1503A, and 78F1506A (flash memory size: 64 KB) are p.83 _†
used, be sure to set bit 0 (MAA) of this register to 0.
Internal data
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for pp.83, _†
memory space fetching instructions or as a stack area.
89, 90
While using the self-programming function, the area of FFE20H to FFEFFH cannot pp.83, _†
be used as a stack memory.
89
SFR: Special Do not access addresses to which SFRs are not assigned.
pp.84, _†
function register
93
area
2nd SFR:
Do not access addresses to which 2nd SFRs are not assigned.
pp.84, _†
Extended special
99
function register
Processor SP: Stack
Since reset signal generation makes the SP contents undefined, be sure to initialize p.89 _†
registers pointer
the SP before using the stack.
Port
P00/CAPH,
To use P00/CAPH, P01/CAPL, and P02/VLC3 as a general-purpose port, set bit 5 p.130 _†
functions P01/CAPL,
(MDSET1) and bit 4 (MDSET0) of LCD mode register (LCDMD) to “0”, which is the
P02/VLC3
same as their default status setting.
P10/SCK20/
To use P10/SCK20/SCL20 and P11/SI20/RxD2/SDA20/INTP6 as a general-purpose p.133 _†
SCL20,
port, note the serial array unit 1 setting. For details, refer to Table 14-9 Relationship
P11/SI20/RxD2/ Between Register Settings and Pins (Channel 0 of unit 1: CSI20, UART2 Reception,
SDA20/INTP6 IIC20).
P12/TO02/SO20/ To use P12/TO02/SO20/TxD2 as a general-purpose port, set bit 2 (TO02) of timer p.133 _†
TxD2
output register 0 (TO0) and bit 2 (TOE02) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting. And as a general-purpose port,
note the serial array unit 1 setting. For details of serial array unit 1 setting, refer to
Table 14-9 Relationship Between Register Settings and Pins (Channel 0 of unit 1:
CSI20, UART2 Reception, IIC20).
P13/TO04/SO10 To use P13/TO04/SO10/TxD1 as a general-purpose port, set bit 4 (TO04) of timer p.133 _†
/TxD1
output register 0 (TO0) and bit 4 (TOE04) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting. And as a general-purpose port,
note the serial array unit 0 setting. For details of serial array unit 0 setting, refer to
Table 14-7 Relationship Between Register Settings and Pins (Channel 2 of unit 0:
CSI10, UART1 Transmission, IIC10)
R01UH0004EJ0501 Rev.5.01
959
Jun 20, 2011