UPD78F1502AGK-GAK-AX Datasheet, PDF (979/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(7/39)
Page
Clock
OSTC:
The X1 clock oscillation stabilization wait time does not include the time until clock p.213 _†
generator Oscillation
oscillation starts (“a” below).
stabilization time
counter status
register
OSTS:
To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS p.214 _†
Oscillation
register before executing the STOP instruction.
stabilization time Setting the oscillation stabilization time to 20 μs or less is prohibited.
p.214 _†
select register _{To change the setting of the OSTS register, be sure to confirm that the counting p.214 †}
operation of the OSTC register has been completed.
Do not change the value of the OSTS register during the X1 clock oscillation p.214 _†
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time _{p.214 †}
set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than the count value which is to be checked by the OSTC register after the
oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
The X1 clock oscillation stabilization wait time does not include the time until clock p.214 _†
oscillation starts (“a” below).
CKC: System
clock control
register
The clock set by CSS, MCM0, SDIV, and MDIV2 to MDIV0 is supplied to the CPU _{p.216 †}
and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied
to peripheral hardware (except the real-time counter, timer array unit (when fSUB/2,
fSUB/4, the valid edge of TI0mn input, or the valid edge of INTRTCI is selected as the
count clock), clock output/buzzer output, and watchdog timer) is also changed at the
same time. Consequently, stop each peripheral function when changing the
CPU/peripheral operating hardware clock.
If the peripheral hardware clock is used as the subsystem clock, the operations of the _{p.216 †}
A/D converter and IICA are not guaranteed. For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as well as CHAPTER 31 ELECTRICAL SPECIFICATIONS.
DSCCTL: 20
MHz internal
high-speed
oscillation
20 MHz internal oscillation can only be used if VDD ≥ 2.7 V.
p.218 _†
Set SELDSC when 100 μs have elapsed after having set DSCON with VDD ≥ 2.7 V. p.218 _†
The internal high-speed oscillator must be operated (HIOSTOP = 0) when DSCON = 1. p.218 _†
control register
OSMC:
Write “1” to FSEL before the following two operations.
p.221 _†
Operation speed • Changing the clock prior to dividing fCLK to a clock other than fIH.
mode control • Operating the DMA controller.
register
The CPU waits (140.5 clock (fCLK)) when “1” is written to the FSEL bit.
p.221 _†
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of fX can continue even while the
CPU is waiting.
To increase fCLK to 10 MHz or higher, set FSEL to “1”, then change fCLK after two or p.221 _†
more clocks have elapsed.
Confirm that the clock is operating at 10 MHz or less before setting FSEL = 0.
p.221 _†
R01UH0004EJ0501 Rev.5.01
963
Jun 20, 2011