UPD78F1502AGK-GAK-AX Datasheet, PDF (598/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-4. Format of Slave Address Register (SVA)
Address: F0234H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
SVA
A6
A5
A4
A3
A2
A1
A0
0^Note
Note Bit 0 is fixed to 0.
(3) SO latch
The SO latch is used to retain the SDA0 pin’s output level.
(4) Wakeup controller
This circuit generates an interrupt request (INTIICA) when the address received by this register matches the
address value set to the slave address register (SVA) or when an extension code is received.
(5) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify
that 8-bit data was transmitted or received.
(6) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIICA).
An I²C interrupt request is generated by the following two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM bit)
• Interrupt request generated when a stop condition is detected (set by SPIE bit)
Remark WTIM bit: Bit 3 of IICA control register 0 (IICCTL0)
SPIE bit: Bit 4 of IICA control register 0 (IICCTL0)
(7) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
(8) Serial clock wait controller
This circuit controls the wait timing.
(9) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(10) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
(11) Start condition generator
This circuit generates a start condition when the STT bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY
bit = 1), start condition requests are ignored and the STCF bit is set to 1.
(12) Stop condition generator
This circuit generates a stop condition when the SPT bit is set to 1.
R01UH0004EJ0501 Rev.5.01
582
Jun 20, 2011