UPD78F1502AGK-GAK-AX Datasheet, PDF (632/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.15 Cautions
(1) When STCEN = 0
Immediately after I²C operation is enabled (IICE = 1), the bus communication status (IICBSY = 1) is recognized
regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a
master device communication mode, first generate a stop condition to release the bus, then perform master device
communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IICA control register 1 (IICCTL1).
<2> Set bit 7 (IICE) of IICA control register 0 (IICCTL0) to 1.
<3> Set bit 0 (SPT) of IICCTL0 to 1.
(2) When STCEN = 1
Immediately after I²C operation is enabled (IICE = 1), the bus released status (IICBSY = 0) is recognized
regardless of the actual bus status. To generate the first start condition (STT = 1), it is necessary to confirm that
the bus has been released, so as to not disturb other communications.
(3) If other I²C communications are already in progress
If I²C operation is enabled and the device participates in communication already in progress when the SDA0 pin is
low and the SCL0 pin is high, the macro of I²C recognizes that the SDA0 pin has gone low (detects a start
condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this
interferes with other I²C communications. To avoid this, start I²C in the following sequence.
<1> Clear bit 4 (SPIE) of IICCTL0 to 0 to disable generation of an interrupt request signal (INTIICA) when the stop
condition is detected.
<2> Set bit 7 (IICE) of IICCTL0 to 1 to enable the operation of I²C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL) of IICCTL0 to 1 before ACK is returned (4 to 80 clocks after setting IICE to 1), to forcibly
disable detection.
(4) Setting STT and SPT (bits 1 and 0 of IICCTL0) again after they are set and before they are cleared to 0 is
prohibited.
(5) When transmission is reserved, set SPIE (bit 4 of IICTL0) to 1 so that an interrupt request is generated when the
stop condition is detected. Transfer is started when communication data is written to IICA after the interrupt request
is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait
state because the interrupt request is not generated when communication is started. However, it is not necessary
to set SPIE to 1 when MSTS (bit 7 of IICS) is detected by software.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011