UPD78F1502AGK-GAK-AX Datasheet, PDF (696/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 16 LCD CONTROLLER/DRIVER
<9> Set (SCOC = 1) the SCOC bit (bit 6 of the LCDM register).
Non-selected waveforms are output from all the segment and common pins, and the non-display status is
entered.
<10> Start output corresponding to each data memory by setting (LCDON = 1) the LCDON bit (bit 7 of the LCDM
register).
Caution When stopping the operation of the capacitor split circuit, be sure to set SCOC and LCDON to 0
before setting VLCON to 0.
16.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment
signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the potential difference
becomes lower than VLCD.
Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this problem,
this LCD panel is driven by AC voltage.
(1) Common signals
Each common signal is selected sequentially according to a specified number of time slices at the timing listed in
Table 16-3. In the static display mode, the same signal is output to COM0 to COM3.
In the two-time-slice mode, leave the COM2 and COM3 pins open. In the three-time-slice mode, leave the COM3
pin open.
Use the COM4 to COM7 pins other than in the eight-time-slice mode as open or segment pins.
COM Signal
Number of
Time Slices
Static display mode
Two-time-slice mode
Three-time-slice mode
Four-time-slice mode
Eight-time-slice mode
COM0
Table 16-3. COM Signals
COM1
COM2
COM3
COM4
Open
Open
Open
Note
Note
Note
Note
COM5
Note
Note
Note
Note
COM6
Note
Note
Note
Note
COM7
Note
Note
Note
Note
Note Use the pins as open or segment pins.
R01UH0004EJ0501 Rev.5.01
680
Jun 20, 2011