UPD78F1502AGK-GAK-AX Datasheet, PDF (789/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 21 STANDBY FUNCTION
CHAPTER 21 STANDBY FUNCTION
21.1 Standby Function and Configuration
21.1.1 Standby function
The standby function is mounted onto all 78K0R/Lx3 microcontroller products.
The standby function reduces the operating current of the system, and the following two modes are available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-
speed system clock oscillator, internal high-speed oscillator, 20 MHz internal high-speed oscillator, or subsystem
clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the
operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting
operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released
when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt
request generation.
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set
are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
STOP mode cannot be set while the CPU operates with the subsystem clock. The HALT mode
can be used when the CPU is operating on either the main system clock or the subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating
with main system clock before executing STOP instruction.
3. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter
mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the STOP
instruction.
4. It can be selected by the option byte whether the internal low-speed oscillator continues oscillating or
stops in the HALT or STOP mode. For details, see CHAPTER 26 OPTION BYTE.
5. The STOP instruction cannot be executed when the CPU operates on the 20 MHz internal high-
speed oscillation clock. Be sure to execute the STOP instruction after shifting to internal high-
speed oscillation clock operation.
21.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
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Jun 20, 2011