UPD78F1502AGK-GAK-AX Datasheet, PDF (977/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(5/39)
Page
Port
Port 11
Make the AVDD1 pin the same potential as the EVDD or VDD pin when port 11 is used p.167 _†
functions
as a digital port.
P121 to P124 The function setting on P121 to P124 is available only once after the reset release. p.168 _†
The port once set for connection to an oscillator cannot be used as an input port
unless the reset is performed.
Port 15
Make the AVDD0 pin the same potential as the EVDD or VDD pin when port 15 is used p.176 _†
as a digital port.
Port mode
Be sure to set bits 3 to 7 of PM0, bits 6, 7 of PM1, bit 7 of PM2, bits 4 to 7 of PM3, p.181 _†
register
bits 2 to 7 of PM4, bits 3 to 7 of PM9, bits 1 to 7 of PM10, bits 2 to 7 of PM11, bits 1
(78K0R/LF3) to 7 of PM12, and bits 0 to 6 of PM15 to 1.
Port mode
Be sure to set bits 3 to 7 of PM0, bit 7 of PM1, bits 5 to 7 of PM3, bits 2 to 7 of PM4, p.182 _†
register
bits 2 to 7 of PM6, bits 3 to 7 of PM8, bits 1 to 7 of PM10, bits 2 to 7 of PM11, bits 1
(78K0R/LG3) to 7 of PM12, and bits 3 to 6 of PM15 to 1.
Port mode
Be sure to set bits 3 to 7 of PM0, bits 5 to 7 of PM3, bits 2 to 7 of PM4, bits 2 to 7 of p.183 _†
register
PM6, bits 3 to 7 of PM10, bits 2 to 7 of PM11, bits 1 to 7 of PM12, and bits 3 to 6 of
(78K0R/LH3) PM15 to 1.
ADPC: A/D port Set the channel used for A/D conversion to the input mode by using port mode p.193 _†
configuration registers 2 and 15 (PM2, PM15).
register
Do not set the pin that is set by ADPC as digital I/O by analog input channel p.193 _†
specification register (ADS).
PFALL: Port
For 78K0R/LF3, bits 3 and 7 must be set to 0. For 78K0R/LG3 and 78K0R/LH3, bit 7 p.195 _†
function register must be set to 0.
ISC: Input switch Be sure to clear bits 5 to 7 to “0”.
p.196 _†
control register
1-bit
When a 1-bit manipulation instruction is executed on a port that provides both input p.205 _†
manipulation and output functions, the output latch value of an input port that is not subject to
instruction for manipulation may be written in addition to the targeted bit. Therefore, it is
port register n recommended to rewrite the output latch when switching a port from input mode to
(Pn)
output mode.
Clock
CMC: Clock
CMC can be written only once after reset release, by an 8-bit memory manipulation p.210 _†
generator operation mode instruction.
control register After reset release, set CMC before X1 or XT1 oscillation is started as set by the p.210 _†
clock operation status control register (CSC).
Be sure to set AMPH to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
p.210 _†
To use CMC with its initial value (00H), be sure to set it to 00H after releasing reset in p.210 _†
order to prevent malfunction when a program loop occurs.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011