UPD78F1502AGK-GAK-AX Datasheet, PDF (824/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
(2) Low-voltage detection level select register (LVIS)
This register selects the low-voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 0EH.
Figure 24-3. Format of Low-Voltage Detection Level Select Register (LVIS)
Address: FFFAAH After reset: 0EH ^Note R/W
Symbol
7
6
5
4
LVIS
0
0
0
0
3
LVIS3
2
LVIS2
1
LVIS1
0
LVIS0
LVIS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LVIS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LVIS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LVIS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Detection level
VLVI0 (4.22 ±0.1 V)
VLVI1 (4.07 ±0.1 V)
VLVI2 (3.92 ±0.1 V)
VLVI3 (3.76 ±0.1 V)
VLVI4 (3.61 ±0.1 V)
VLVI5 (3.45 ±0.1 V)
VLVI6 (3.30 ±0.1 V)
VLVI7 (3.15 ±0.1 V)
VLVI8 (2.99 ±0.1 V)
VLVI9 (2.84 ±0.1 V)
VLVI10 (2.68 ±0.1 V)
VLVI11 (2.53 ±0.1 V)
VLVI12 (2.38 ±0.1 V)
VLVI13 (2.22 ±0.1 V)
VLVI14 (2.07 ±0.1 V)
VLVI15 (1.91 ±0.1 V)
Note The reset value changes depending on the reset source.
If the LVIS register is reset by LVI, it is not reset but holds the current value. The value of this register is
reset to “0EH” if a reset other than by LVI is effected.
Cautions 1. Be sure to clear bits 4 to 7 to “0”.
R01UH0004EJ0501 Rev.5.01
808
Jun 20, 2011