UPD78F1502AGK-GAK-AX Datasheet, PDF (287/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Table 6-4. Operations from Count Operation Enabled State to TCRmn Count Start
Timer operation mode
• Interval timer mode
• Event counter mode
• Capture mode
• One-count mode
• Capture & one-count mode
Operation when TSmn = 1 is set
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of TDRmn to TCRmn and the subsequent
count clock performs count down operation (see 6.3 (6) (a) Start timing in
interval timer mode).
Writing 1 to TSmn bit loads the value of TDRmn to TCRmn.
The subsequent count clock performs count down operation.
The external trigger detection selected by STSmn2 to STSmn0 bits in the
TMRmn register does not start count operation (see 6.3 (6) (b) Start timing in
event counter mode).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRmn and the subsequent count clock
performs count up operation (see 6.3 (6) (c) Start timing in capture mode).
When TEmn = 0, writing 1 to TSmn bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of TDRmn to TCRmn and the subsequent
count clock performs count down operation (see 6.3 (6) (d) Start timing in one-
count mode).
When TEmn = 0, writing 1 to TSmn bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRmn and the subsequent count clock
performs count up operation (see 6.3 (6) (e) Start timing in capture & one-
count mode).
Cautions 1. Channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 can
be set only to the interval mode.
2. Channel 6 of timer array unit 0 of the 78K0R/LF3 can be set only to the interval mode and
one-count mode (when using as master).
3. Channels 0 to 3 of timer array unit 1 of the 78K0R/LG3 can be set only to the interval mode.
(a) Start timing in interval timer mode
<1> Writing 1 to TSmn sets TEmn = 1
<2> The write data to TSmn is held until count clock generation.
<3> TCRmn holds the initial value until count clock generation.
<4> On generation of count clock, the “TDRmn value” is loaded to TCRmn and count starts.
Remark mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011