UPD78F1502AGK-GAK-AX Datasheet, PDF (629/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-25 shows the communication reservation timing.
Figure 15-25. Communication Reservation Timing
Program processing STT = 1
Communi-
Hardware processing cation
reservation
Write to
IICA
Set SPD
and
INTIICA
Set
STD
SCL0
123456789
1
2
3
4
5
6
SDA0
Generate by master device with bus mastership
Remark
IICA:
STT:
STD:
SPD:
IICA shift register
Bit 1 of IICA control register 0 (IICCTL0)
Bit 1 of IICA status register (IICS)
Bit 0 of IICA status register (IICS)
Communication reservations are accepted via the timing shown in Figure 15-26. After bit 1 (STD) of the IICA
status register (IICS) is set to 1, a communication reservation can be made by setting bit 1 (STT) of IICA control
register 0 (IICCTL0) to 1 before a stop condition is detected.
Figure 15-26. Timing for Accepting Communication Reservations
SCL0
SDA0
STD
SPD
Standby mode (Communication can be reserved by setting STT to 1 during this period.)
Figure 15-27 shows the communication reservation protocol.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011