UPD78F1502AGK-GAK-AX Datasheet, PDF (695/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 16 LCD CONTROLLER/DRIVER
(2) Internal voltage boosting method
<1> Set the internal voltage boosting method via the MDSET0 and MDSET1 bits (bits 4 and 5 of the LCDMD
register) (MDSET0 = 1, MDSET1 = 0).
<2> To use segment output only pins, use the SEGEN register to enable segment output to them.
To use segment output pins, which are alternatively used with port pins, use the PFALL register to set them
to segment output. In addition, to use the segment output pins, which are alternatively used with the TI04,
TI02, and RxD3 pins, use the ISC register to disable input to the Schmitt trigger buffer.
<3> Set the display data in LCD display RAM.
<4> Set the number of time slices and the bias mode via the LCDM0 to LCDM2 bits (bits 0 to 2 of the LCDM
register).
• When setting Static, 2-time-slice, 3-time-slice, or 4-time-slice → Go to step <5>
• When setting 8-time-slice → Go to step <6>
(Only 1/3 bias mode and 1/4 bias mode can be set for the internal voltage boost method.)
<5> Select the display data area via the LCDSEL and BLON bits (bits 3 and 4 of the LCDM register).
<6> Set the LCD source clock and LCD clock via the LCDC0 register.
<7> Set the reference voltage (adjust the contrast) via the VLCD register.
<8> Wait for the reference voltage setup time (2 ms (min.)) after setting of the VLCD register.
<9> Set (VLCON = 1) the VLCON bit (bit 5 of the LCDM register) to start the voltage boost circuit operation.
<10> Wait for the voltage boost wait time after setting of VLCON (see CHAPTER 31 ELECTRICAL
SPECIFICATIONS).
<11> Set (SCOC = 1) the SCOC bit (bit 6 of the LCDM register).
Non-selected waveforms are output from all the segment and common pins, and the non-display status is
entered.
<12> Start output corresponding to each data memory by setting (LCDON = 1) the LCDON bit (bit 7 of the LCDM
register).
Caution When stopping the operation of the voltage boost circuit, be sure to set SCOC and LCDON to 0
before setting VLCON to 0.
(3) Capacitor split method
<1> Set the capacitor split method via the MDSET0 and MDSET1 bits (bits 4 and 5 of the LCDMD register)
(MDSET0 = 0, MDSET1 = 1).
<2> To use segment output only pins, use the SEGEN register to enable segment output to them.
To use segment output pins, which are alternatively used with port pins, use the PFALL register to set them
to segment output. In addition, to use the segment output pins, which are alternatively used with the TI04,
TI02, and RxD3 pins, use the ISC register to disable input to the Schmitt trigger buffer.
<3> Set the display data in LCD display RAM.
<4> Set the number of time slices and the bias mode via the LCDM0 to LCDM2 bits (bits 0 to 2 of the LCDM
register).
(Only 1/3 bias mode can be set for the capacitor split method)
<5> Select the display data area via the LCDSEL and BLON bits (bits 3 and 4 of the LCDM register).
<6> Set the LCD source clock and LCD clock via the LCDC0 register.
<7> Set (VLCON = 1) the VLCON bit (bit 5 of the LCDM register) to start the voltage reduction circuit operation.
<8> Wait for the voltage capacitor split wait time after setting of VLCON (see CHAPTER 31 ELECTRICAL
SPECIFICATIONS).
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Jun 20, 2011