UPD78F1502AGK-GAK-AX Datasheet, PDF (828/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
Figure 24-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Supply voltage (VDD)
VLVI
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
Set LVI to be
used for reset
LVIMK flag _HNote 1
(set by software)
<1>
LVISEL flag
(set by software) ^L
<2>
LVION flag
(set by software)
<3>
Not
cleared
<4>
<5>Wait time
LVIF flag
LVIMD flag
(set by software)
<6>
Note 2
<7>
Not
cleared
Not cleared
Not cleared
Time
Cleared
Cleared
Cleared
LVIRF flag^{Note 3}
LVI reset signal
POC reset signal
Cleared by
software
Cleared by
software
Internal reset signal
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The LVIIF flag of the interrupt request flag registers and the LVIF flag may be set (1).
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET
FUNCTION.
Remarks 1. <1> to <7> in Figure 24-5 above correspond to <1> to <7> in the description of “When starting
operation” in 24.4.1 (1) (a) When LVI default start function stopped is set (LVIOFF = 1).
2. VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
R01UH0004EJ0501 Rev.5.01
812
Jun 20, 2011