UPD78F1502AGK-GAK-AX Datasheet, PDF (613/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.4.2 Setting transfer clock by using IICWL and IICWH registers
(1) Setting transfer clock on master side
Transfer clock =
fCLK
IICWL + IICWH + fCLK (tR + tF)
At this time, the optimal setting values of IICWL and IICWH are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
IICWL =
0.52
Transfer clock
× fCLK
0.48
IICWH = ( _{Transfer clock} − tR − tF) × fCLK
• When the standard mode
0.47
IICWL = _{Transfer clock} × fCLK
0.53
IICWH = ( _{Transfer clock}
− tR − tF) × fCLK
(2) Setting IICWL and IICWH on slave side
(The fractional parts of all setting values are truncated.)
• When the fast mode
IICWL = 1.3 μs × fCLK
IICWH = (1.2 μs − tR − tF) × fCLK
• When the standard mode
IICWL = 4.7 μs × fCLK
IICWH = (5.3 μs − tR − tF) × fCLK
Caution Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK
operation frequency for serial interface IICA is determined according to the mode.
Fast mode:
fCLK = 3.5 MHz (MIN.)
Standard mode: fCLK = 1 MHz (MIN.)
Remarks 1.
2.
Calculate the rise time (tR) and fall time (tF) of the SDA0 and SCL0 signals separately, because they
differ depending on the pull-up resistance and wire load.
IICWL: IICA low-level width setting register
IICWH: IICA high-level width setting register
tF:
SDA0 and SCL0 signal falling times
tR:
SDA0 and SCL0 signal rising times
fCLK: CPU/peripheral hardware clock frequency
R01UH0004EJ0501 Rev.5.01
597
Jun 20, 2011