UPD78F1502AGK-GAK-AX Datasheet, PDF (662/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.6 Timing Charts
When using the I²C bus mode, the master device outputs an address via the serial bus to select one of several slave
devices as its communication partner.
After outputting the slave address, the master device transmits the TRC bit (bit 3 of the IICA status register (IICS)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 15-32 and 15-33 show timing charts of the data communication.
The IICA shift register (IICA)’s shift operation is synchronized with the falling edge of the serial clock (SCL0). The
transmit data is transferred to the SO latch and is output (MSB first) via the SDA0 pin.
Data input via the SDA0 pin is captured into IICA at the rising edge of SCL0.
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Jun 20, 2011