UPD78F1502AGK-GAK-AX Datasheet, PDF (424/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 10 12-BIT A/D CONVERTER (μ PD78F150xA),
10-BIT A/D CONVERTER (μ PD78F151xA)
(3) Timer trigger mode (Continuous conversion mode)
<1> Timer trigger mode is set and a timer trigger wait state is entered by setting bit 7 (ADTMD) of A/D converter mode
register 1 (ADM1) to 1.
<2> When the timer trigger signal is detected, bit 7 (ADCS) of the A/D converter mode register (ADM) is automatically
set to 1 and A/D conversion of the voltage applied to the analog input pin specified using the analog input
channel specification register (ADS) starts.
<3> When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. When one A/D conversion has
been completed, the next A/D conversion operation is immediately started.
<4> If 1 is written to ADS during A/D conversion, the A/D conversion operation under execution is stopped and
restarted from the beginning. At this time, the conversion result immediately before is retained.
<5> If a timer trigger signal is generated during A/D conversion, the A/D conversion operation under execution is
stopped and restarted from the beginning. At this time, the conversion result immediately before is retained.
<6> If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped, and a timer trigger wait
state is entered. At this time, the conversion result immediately before is retained.
<7> When 0 is written to ADTMD while A/D conversion operation is stopped (ADCS = 0), the software trigger mode is
set and A/D conversion operation is not started, even if a timer trigger signal is generated.
Figure 10-20. Timer trigger mode (Continuous conversion mode)
<1> ADTMD = 1
<7> ADTMD = 0
ADTMD
Timer trigger
<2> Timer trigger generation
Note
<5> Timer trigger generation
<6> ADCS = 0
ADCS
A/D conversion
<3> A/D conversion
<3> A/D conversion
is completed
<3> A/D conversion
is completed
is completed
<4> Rewriting ADS
Wait
ANIn
state
ANIn
ANIn
ANIm
ANIm
ANIm
Wait
state
Conversion operation under
execution is stopped, and
restarted from the beginning
Conversion operation under
execution is stopped, and
restarted from the beginning
Conversion operation
under execution is
stopped
ADCR,
ADCRH
ANIn
ANIn
ANIm
INTAD
Note Leave at least enough time for A/D conversion to finish between each generation of the timer trigger signal.
Remark 78K0R/LF3:
n = 0 to 6, 15, m = 0 to 6, 15
78K0R/LG3, 78K0R/LH3: n = 0 to 10, 15, m = 0 to 10, 15
R01UH0004EJ0501 Rev.5.01
408
Jun 20, 2011