UPD78F1502AGK-GAK-AX Datasheet, PDF (640/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
An example of the processing procedure of the slave with the INTIICA interrupt is explained below (processing is
performed assuming that no extension code is used). The INTIICA interrupt checks the status, and the following
operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address does
not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns
from the interrupt (the ready flag is cleared).
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I²C bus
remaining in the wait state.
Remark <1> to <3> above correspond to <1> to <3> in Figure 15-31 Slave Operation Flowchart (2).
Figure 15-31. Slave Operation Flowchart (2)
INTIICA generated
Yes
SPD = 1?
No
Yes
STD = 1?
No
<3>
Set ready flag
<1>
<2>
No
COI = 1?
Yes
Communication direction flag
← TRC
Set communication mode flag
Clear ready flag
Clear communication direction
flag, ready flag, and
communication mode flag
Interrupt servicing completed
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Jun 20, 2011