UPD78F1502AGK-GAK-AX Datasheet, PDF (783/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 19 INTERRUPT FUNCTIONS
19.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE =
1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore,
to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to
enable interrupt acknowledgment.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for multiple interrupt servicing.
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently
being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that
of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt
servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they
have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is
acknowledged following execution of at least one main processing instruction execution.
Table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 19-17
shows multiple interrupt servicing examples.
Table 19-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Multiple Interrupt Request
Interrupt Being Serviced
Maskable interrupt
ISP1 = 0
ISP0 = 0
ISP1 = 0
ISP0 = 1
ISP1 = 1
ISP0 = 0
ISP1 = 1
ISP0 = 1
Software interrupt
Priority Level 0
(PR = 00)
IE = 1 IE = 0
{
×
{
×
{
×
{
×
{
×
Maskable Interrupt Request
Priority Level 1
(PR = 01)
Priority Level 2
(PR = 10)
IE = 1 IE = 0 IE = 1 IE = 0
×
×
×
×
{
×
×
×
{
×
{
×
{
×
{
×
{
×
{
×
Priority Level 3
(PR = 11)
IE = 1 IE = 0
×
×
×
×
×
×
{
×
{
×
Software
Interrupt
Request
{
{
{
{
{
Remarks 1. {: Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. ISP0, ISP1, and IE are flags contained in the PSW.
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced.
ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced.
ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced.
ISP1 = 1, ISP0 = 1: Wait for An interrupt acknowledgment.
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
4. PR is a flag contained in PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, and PR12H.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 1 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
R01UH0004EJ0501 Rev.5.01
767
Jun 20, 2011