UPD78F1502AGK-GAK-AX Datasheet, PDF (808/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 22 RESET FUNCTION
Table 22-1. Operation Statuses During Reset Period
Item
System clock
Main system clock fIH
fX
fEX
Subsystem clock fXT
fIL
CPU
Flash memory
RAM
Port (latch)
Timer array unit (TAU)
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Operational amplifier
Voltage reference
Serial array unit (SAU)
Serial interface (IICA)
LCD controller/driver
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt
BCD correction circuit (BCD)
During Reset Period
Clock supply to the CPU is stopped.
Operation stopped
Operation stopped (X1 and X2 pins are input port mode)
Clock input invalid (pin is input port mode)
Operation stopped (XT1 and XT2 pins are input port mode)
Operation stopped
Operation stopped (The value, however, is retained when the voltage is at least the power-on-
clear detection voltage.)
Set P130 to low-level output. The port pins except for P130 become high impedance.
Operation stopped
Operation stopped
(COM only pin, SEG only pin, COM/SEG alternate pin: GND output, SEG/general-purpose port
alternate pin: input port, VLC0 to VLC2 pins: high-impedance output, VLC3/P02 pin, CAPH/P00 pin,
CAPL/P01 pin: input port)
Operation stopped
Detection operation possible
Operation stopped (however, operation continues at LVI reset)
Operation stopped
Remarks 1.
2.
fIH: Internal high-speed oscillation clock,
fX: X1 oscillation clock
fEX: External main system clock,
fXT: XT1 oscillation clock
fIL: Internal low-speed oscillation clock
The functions mounted depend on the product. Refer to 1.4 Block Diagram and 1.5
Functions.
Outline of
R01UH0004EJ0501 Rev.5.01
792
Jun 20, 2011