UPD78F1502AGK-GAK-AX Datasheet, PDF (741/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
18.4.2 Transfer mode
The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of the DMCn register.
DRSn
0
0
1
1
DSn
DMA Transfer Mode
0
Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)
1
Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2)
0
Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address)
1
Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address)
By using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface,
data resulting from A/D conversion can be consecutively transferred, and port data can be scanned at fixed time intervals
by using a timer.
18.4.3 Termination of DMA transfer
When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request
(INTDMAn) is generated and transfer is terminated.
When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, the DBCn and DRAn registers hold the value
when transfer is terminated.
The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated.
Remark n: DMA channel number (n = 0, 1)
18.5 Example of Setting of DMA Controller
18.5.1 CSI consecutive transmission
A flowchart showing an example of setting for CSI consecutive transmission is shown below.
• Consecutive transmission of CSI10
• DMA channel 0 is used for DMA transfer.
• DMA start source: INTCSI10 (software trigger (STG0) only for the first start source)
• Interrupt of CSI10 is specified by IFC03 to IFC00 (bits 3 to 0 of the DMC0 register) = 1000B.
• Transfers FFB00H to FFBFFH (256 bytes) of RAM to FFF44H of the transmit buffer (SIO10) of CSI.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011