UPD78F1502AGK-GAK-AX Datasheet, PDF (998/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(26/39)
Page
LCD
LCDM: LCD
To manipulate VLCON when using the internal voltage boosting method or capacitor p.669 _†
controller/d display mode split method, follow the procedure below.
river
register
A. To stop the operation of the voltage boosting/capacitor split circuit after switching
display status from on to off:
1) Set to display off status by setting LCDON = 0.
2) Disable outputs of all the segment buffers and common buffers by setting
SCOC = 0.
3) Stop the operation of the voltage boosting/capacitor split circuit by setting
V LCON = 0.
B. To stop the operation of the voltage boosting/capacitor split circuit during display
on status:
Setting prohibited. Be sure to stop the operation of the voltage
boosting/capacitor split circuit after setting display off.
C. To set display on from stop status of the voltage boosting/capacitor split circuit:
1) Start the operation of the voltage boosting/capacitor split circuit by setting
VLCON = 1, then wait for the voltage boosting/capacitor split wait time (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
2) Set all the segment buffers and common buffers to non-display output
status by setting SCOC = 1.
3) Set display on by setting LCDON = 1.
LCDC0: LCD Bits 3, 6, and 7 must be set to 0.
p.670 _†
clock control
Set the LCD clock (LCDCL) to no more than 512 Hz when the internal voltage boost p.670 _†
register 0
method has been set.
VLCD: LCD
The VLCD setting is valid only when the voltage boost circuit is operating.
p.671 _†
boost level
Bits 5 to 7 must be set to 0.
p.671 _†
control register Be sure to change the VLCD value after having stopped the operation of the voltage p.671 _†
boost circuit (VLCON = 0).
These values above may change after device evaluation.
p.671 _†
To use the internal voltage boosting method, specify the reference voltage by using p.671 _†
the VLCD register (or perform a reset to use the default value of the reference
voltage), wait for the reference voltage setup time (2 ms (min.)), and then set VLCON
to 1.
PFALL: Port
For 78K0R/LF3, bits 3 and 7 must be set to 0. For 78K0R/LG3 and 78K0R/LH3, bit 7 p.672 _†
function register must be set to 0.
SEGEN:
SEGEN can be written only once after reset release.
p.673 _†
Segment enable For 78K0R/LF3, bits 1 to 7 must be set to 0. For 78K0R/LG3, bits 2 to 7 must be set p.673 _†
register
to 0. For 78K0R/LH3, bits 5 to 7 must be set to 0.
R01UH0004EJ0501 Rev.5.01
982
Jun 20, 2011