UPD78F1502AGK-GAK-AX Datasheet, PDF (740/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
18.4 Operation of DMA Controller
18.4.1 Operation procedure
<1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set
DENn to 1. Use 80H to write with an 8-bit manipulation instruction.
<2> Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer to the
DSAn, DRAn, DBCn, and DMCn registers.
<3> The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation
instruction.
<4> When a software trigger (STGn) or a start source trigger specified by IFCn3 to IFCn0 is input, a DMA transfer is
started.
<5> Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer is
automatically terminated by occurrence of an interrupt (INTDMAn).
<6> Stop the operation of the DMA controller by clearing DENn to 0 when the DMA controller is not used.
Figure 18-6. Operation Procedure
DENn = 1
Setting DSAn, DRAn, DBCn, and DMCn
Set by software program
DSTn = 1
DMA trigger = 1?
Yes
Transmitting DMA request
Receiving DMA acknowledge
DMA transfer
DRAn = DRAn + 1 (or + 2)
DBCn = DBCn − 1
DBCn = 0000H ?
Yes
DSTn = 0
INTDMAn = 1
No
Operation by DMA
controller (hardware)
No
DENn = 0
Remark n: DMA channel number (n = 0, 1)
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
Set by software program
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