UPD78F1502AGK-GAK-AX Datasheet, PDF (265/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
5.6.7 Time required for switchover of CPU clock and main system clock
By setting bits 0 to 2, 4, and 6 (MDIV0 to MDIV2, SDIV, MCM0, CSS) of the system clock control register (CKC), the
CPU clock can be switched (between the main system clock and the subsystem clock), main system clock can be
switched (between the internal high-speed oscillation clock and the high-speed system clock), and the division ratio of the
main system clock can be changed.
The actual switchover operation is not performed immediately after rewriting to CKC; operation continues on the pre-
switchover clock for several clocks (see Table 5-6 to Table 5-9).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of
CKC. Whether the main system clock is operating on the high-speed system clock or internal high-speed oscillation clock
can be ascertained using bit 5 (MCS) of CKC.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Internal high-speed oscillation clock
Table 5-6. Maximum Time Required for Main System Clock Switchover
Clock A
fMAINC
fSUBC
fIH
fMAINC
Switching directions
(changing the division ratio)
Clock B
fMAINC
fSUBC
fMX
fSUBC
Remark
see Table 5-7
see Table 5-8
see Table 5-9
Table 5-7. Maximum Number of Clocks Required in fMAINC ↔fMAINC (changing the division ratio),
fSUBC ↔fSUBC (changing the division ratio)
Set Value Before Switchover
Clock A
Clock B
Set Value After Switchover
Clock A
Clock B
1 + fA/fB clock
1 + fB/fA clock
Table 5-8. Maximum Number of Clocks Required in fIH ↔fMX
Set Value Before Switchover
MCM0
0
(fMAIN = fIH)
1
(fMAIN = fMX)
fMX≥fIH
fMX<fIH
fMX≥fIH
fMX<fIH
Set Value After Switchover
MCM0
0
1
(fMAIN = fIH)
(fMAIN = fMX)
1 + fIH/fMX clock
2fIH/fMX clock
2fMX/fIH clock
1 + fMX/fIH clock
(Remarks are listed on the next page.)
R01UH0004EJ0501 Rev.5.01
249
Jun 20, 2011