UPD78F1502AGK-GAK-AX Datasheet, PDF (259/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/6)
(6) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register CMC Register^Note
Status Transition
OSCSELS
(B) → (D)
1
CSC Register
XTSTOP
0
Waiting for
Oscillation
Stabilization
Necessary
CKC Register
CSS
1
Unnecessary if the CPU is operating
with the subsystem clock
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
(7) CPU clock changing from internal high-speed oscillation clock (B) to 20 MHz internal high-speed oscillation
clock (J)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (J)
DSCCTL Register ^Note
DSCON
1
Waiting for Oscillation
Stabilization
Necessary (100 μs)
DSCCTL Register
SELDSC
1
Unnecessary if the CPU is operating with the 20 MHz
internal high-speed oscillation clock
Note Check that VDD ≥ 2.7 V and set DSCON = 1.
(8) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (B)
CSC Register
HIOSTOP
0
Oscillation accuracy
stabilization time
10 μ s
CKC Register
MCM0
0
Unnecessary if the
CPU is operating with
the internal high-
speed oscillation
clock
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011