UPD78F1502AGK-GAK-AX Datasheet, PDF (232/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
(5) System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a division ratio.
CKC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 09H.
Figure 5-6. Format of System Clock Control Register (CKC)
Address: FFFA4H After reset: 09H R/W^{Note 1}
Symbol
<7>
<6>
<5>
CKC
CLS
CSS
MCS
<4>
MCM0
3
SDIV
2
MDIV2
1
MDIV1
0
MDIV0
CLS
0
1
Status of CPU/peripheral hardware clock (fCLK)
Main system clock (fMAIN)
Subsystem clock (fSUB)
MCS
0
1
Status of Main system clock (fMAIN)
Internal high-speed oscillation clock (fIH) or 20 MHz internal high-speed oscillation clock
(fIH20)
High-speed system clock (fMX)
CSS
0
0
1 ^{Note 4}
MCM0
0
1
× ^{Note 4}
SDIV
MDIV2
×
0
×
0
×
0
×
0
×
1
×
1
×
0
×
0
×
0
×
0
×
1
×
1
0
×
1
×
Other than above
MDIV1
0
0
1
1
0
0
0
0
1
1
0
0
×
×
MDIV0
0
1
0
1
0
1
0
1
0
1
0
1
×
×
Selection of
CPU/peripheral
hardware clock (fCLK)
fIH
fIH/2 (default)
fIH/2²
fIH/2³
f /2^{4 Note 2}
IH
f /2^{5 Note 2}
IH
fMX
fMX/2
fMX/2²
fMX/2³
fMX/2⁴
f /2^{5 Note 3}
MX
fSUB
fSUB/2
Setting prohibited
Notes 1. Bits 7 and 5 are read-only.
2. Setting is prohibited when fIH = 1 MHz.
3. Setting is prohibited when fMX < 4 MHz.
4. Changing the value of the MCM0 bit is prohibited while CSS is set to 1.
(Remarks and Cautions are listed on the next page.)
R01UH0004EJ0501 Rev.5.01
216
Jun 20, 2011