UPD78F1502AGK-GAK-AX Datasheet, PDF (842/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
Operation example 2: When used as interrupt
Interrupt requests may be generated frequently.
Take the following action.
<Action>
Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the falling edge of VDD, or “supply
voltage (VDD) < detection voltage (VLVI)” when detecting the rising edge of VDD, in the servicing routine of the LVI
interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt request
flag register 0L (IF0L) to 0.
For a system with a long supply voltage fluctuation period near the LVI detection voltage, take the above action
after waiting for the supply voltage fluctuation time.
Remark
If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above words
change as follows.
• Supply voltage (VDD) → Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
(2) Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
There is some delay from the time supply voltage (VDD) < LVI detection voltage (VLVI) until the time LVI reset has been
generated.
In the same way, there is also some delay from the time LVI detection voltage (VLVI) ≤ supply voltage (VDD) until the
time LVI reset has been released (see Figure 24-12).
Figure 24-12. Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
Supply voltage (VDD)
VLVI
LVIF flag
<1>
LVI reset signal
<1>: Minimum pulse width (200 μs (MIN.))
R01UH0004EJ0501 Rev.5.01
Jun 20, 2011
Time
<1>
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