UPD78F1502AGK-GAK-AX Datasheet, PDF (1003/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(31/39)
Page
Standby
function
Reset
function
OSTS:
The X1 clock oscillation stabilization wait time does not include the time until clock p.775 _†
Oscillation
oscillation starts (“a” below).
stabilization time
select register
STOP mode
Because the interrupt request signal is used to clear the standby mode, if there is an p.782 _†
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
The STOP instruction cannot be executed when the CPU operates on the 20 MHz pp.782 _†
internal high-speed oscillation clock. Be sure to execute the STOP instruction after , 784
shifting to internal high-speed oscillation clock operation.
To use the peripheral hardware that stops operation in the STOP mode, and the p.784 _†
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
To stop the internal low-speed oscillation clock in the STOP mode, use an option p.784 _†
byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0
(WDSTBYON) of 000C0H = 0), and then execute the STOP instruction.
To shorten oscillation stabilization time after the STOP mode is released when the p.784 _†
CPU operates with the high-speed system clock (X1 oscillation), temporarily switch
the CPU clock to the internal high-speed oscillation clock before the next execution
of the STOP instruction. Before changing the CPU clock from the internal high-
speed oscillation clock to the high-speed system clock (X1 oscillation) after the
STOP mode is released, check the oscillation stabilization time with the oscillation
stabilization time counter status register (OSTC).
−
For an external reset, input a low level for 10 μs or more to the RESET pin
p.788 _†
(To perform an external reset upon power application, a low level of at least 10 μs
must be continued during the period in which the supply voltage is within the
operating range (VDD ≥ 1.8 V)).
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and p.788 _†
internal low-speed oscillation clock stop oscillating. External main system clock input
becomes invalid.
When the STOP mode is released by a reset, the RAM contents in the STOP mode p.788 _†
are held during reset input.
When reset is effected, port pin P140 is set to low-level output and other port pins p.788 _†
become high-impedance, because each SFR and 2nd SFR are initialized.
Block diagram of An LVI circuit internal reset does not reset the LVI circuit.
p.790 _†
reset function
Watchdog timer A watchdog timer internal reset resets the watchdog timer.
p.790 _†
overflow
RESF: Reset Do not read data by a 1-bit memory manipulation instruction.
p.797 _†
control flag
Do not make a judgment based on only the read value of the RESF register 8-bit p.797 _†
register
data, because bits other than TRAP, WDRF, and LVIRF become undefined.
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF p.797 _†
flag may become 1 from the beginning depending on the power-on waveform.
R01UH0004EJ0501 Rev.5.01
987
Jun 20, 2011