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UPD78F1502AGK-GAK-AX Datasheet, PDF (460/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers
78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(1) Shift register
This is an 8-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8 bits of serial data register mn (SDRmn).
Shift register
76543210
(2) Lower 8 bits of the serial data register mn (SDRmn)
SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive buffer
register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK).
When data is received, parallel data converted by the shift register is stored in the lower 8 bits. When data is to be
transmitted, set transmit to be transferred to the shift register to the lower 8 bits.
The data stored in the lower 8 bits of this register is as follows, depending on the setting of bits 0 to 2 (DLSmn0 to
DLSmn2) of the SCRmn register, regardless of the output sequence of the data.
• 5-bit data length (stored in bits 0 to 4 of SDRmn register) (settable in UART mode only)
• 7-bit data length (stored in bits 0 to 6 of SDRmn register)
• 8-bit data length (stored in bits 0 to 7 of SDRmn register)
SDRmn can be read or written in 16-bit units.
The lower 8 bits of SDRmn of SDRmn can be read or writtenNote as the following SFR, depending on the
communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IICr communication … SIOr (IICr data register)
Note Writing in 8-bit units is prohibited
when the operation is stopped
(SEmn = 0).
Reset signal generation clears this register to 0000H.
Remarks 1. After data is received, “0” is stored in bits 0 to 7 in bit portions that exceed the data length.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p: CSI number (p = 00, 01, 10, 20), q: UART number (q = 0 to 3), r: IIC number (r = 10, 20)
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011