UPD78F1502AGK-GAK-AX Datasheet, PDF (830/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
Figure 24-6. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 0)
Interrupt operation mode is set
by setting LVIMD to 0
(LVI interrupt is masked)
Change LVI
detection
voltage (VLVI)
Reset mode is set
by setting LVIMD to 1
Supply voltage (VDD)
VLVI value after a change
VLVI = 2.07 V (TYP.)
VPOR = 1.61 V (TYP.)
VPDR = 1.59 V (TYP.)
LVIMK flag
(set by software)
H^{Note 1}
LVISEL flag
(set by software)
L
LVION flag
H
(set by software)
Not
cleared
Not cleared
Time
LVIF flag
LVIMD flag
H
(set by software)
LVIRF flag
Note 2
Not
cleared
Not cleared
Cleared
Cleared
LVI reset signal
POC reset signal
Cleared by
software
Cleared by
software
Cleared by
software
Internal reset signal
Notes 1.
2.
The LVIMK flag is set to “1” by reset signal generation.
LVIRF is bit 0 of the reset control flag register (RESF).
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the LVIRF flag may become 1
from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 22 RESET FUNCTION.
Remark VPOR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage
R01UH0004EJ0501 Rev.5.01
814
Jun 20, 2011