UPD78F1502AGK-GAK-AX Datasheet, PDF (276/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
(2) Timer data register mn (TDRmn)
This is a 16-bit register from which a capture function and a compare function can be selected.
The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0
bits of TMRmn.
The value of TDRmn can be changed at any time.
This register can be read or written in 16-bit units.
Reset signal generation clears this register to 0000H.
Figure 6-4. Format of Timer Data Register mn (TDRmn)
Address: FFF18H, FFF19H (TDR00), FFF1AH, FFF1BH (TDR01), After reset: 0000H R/W
FFF64H, FFF65H (TDR02) to FFF6EH, FFF6FH (TDR07)
FFF70H, FFF71H (TDR10) to FFF76H, FFF77H (TDR13)
FFF19H (TDR00)
FFF18H (TDR00)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDRmn
(i) When TDRmn is used as compare register
Counting down is started from the value set to TDRmn. When the count value reaches 0000H, an interrupt
signal (INTTMmn) is generated. TDRmn holds its value until it is rewritten.
Caution TDRmn does not perform a capture operation even if a capture trigger is input, when it is set
to the compare function.
(ii) When TDRpq is used as capture register
The count value of TCRpq is captured to TDRpq when the capture trigger is input.
A valid edge of the TIpq pin can be selected as the capture trigger. This selection is made by TMRpq.
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided
with timer I/O pins)
78K0R/LF3: mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011