UPD78F1502AGK-GAK-AX Datasheet, PDF (394/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 8 WATCHDOG TIMER
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending
on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
In HALT mode
In STOP mode
WDSTBYON = 0
Watchdog timer operation stops.
WDSTBYON = 1
Watchdog timer operation continues.
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short,
an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
5. The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM^TM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
8.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts
counting again by writing “ACH” to WDTE during the window open period before the overflow time.
The following overflow time is set.
WDCS2
0
0
0
0
1
1
1
1
Table 8-3. Setting of Overflow Time of Watchdog Timer
WDCS1
0
0
1
1
0
0
1
1
WDCS0
0
1
0
1
0
1
0
1
Overflow Time of Watchdog Timer
(fIL = 33 kHz (MAX.))
2⁷/fIL (3.88 ms)
2⁸/fIL (7.76 ms)
2⁹/fIL (15.52 ms)
2¹⁰/fIL (31.03 ms)
2¹²/fIL (124.12 ms)
2¹⁴/fIL (496.48 ms)
2¹⁵/fIL (992.97 ms)
2¹⁷/fIL (3971.88 ms)
Caution The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow
time and window size taking this delay into consideration.
Remark fIL: Internal low-speed oscillation clock frequency
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011