UPD78F1502AGK-GAK-AX Datasheet, PDF (983/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(11/39)
Page
Timer
array unit
TMRmn: Timer Be sure to clear bits 14, 13, 5, and 4 to “0”.
pp.264 _†
mode register
to 266
mn
Channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the
pp.266, _†
78K0R/LF3 can be set only to the interval mode.
271
Channel 6 of timer array unit 0 of the 78K0R/LF3 can be set only to the interval mode pp.266, _†
and one-count mode (when using as master).
271
Channels 0 to 3 of timer array unit 1 of the 78K0R/LG3 can be set only to the interval pp.266, _†
mode.
271
TSm: Timer
Be sure to clear bits 15 to 8 of TS0 and bits 15 to 4 of TS1 to “0”.
p.270 _†
channel start
register m
Start Timing (In In the first cycle operation of count clock after writing TSmn, an error at a maximum p.272 _†
Interval Timer of one clock is generated since count start delays until count clock has been
Mode)
generated. When the information on count start timing is necessary, an interrupt can
be generated at count start by setting MDmn0 = 1.
Start Timing (In In the first cycle operation of count clock after writing TSpq, an error at a maximum of p.273 _†
Capture Mode) one clock is generated since count start delays until count clock has been generated.
When the information on count start timing is necessary, an interrupt can be
generated at count start by setting MDpq0 = 1.
Start Timing (In An input signal sampling error is generated since operation starts upon start trigger pp.275, _†
One-count Mode detection (The error is one count clock when TIpq is used).
276
and In Capture &
One-count
Mode)
TTm: Timer
Be sure to clear bits 15 to 8 of TT0 and bits 15 to 4 of TT1 to “0”.
p.277 _†
channel stop
register m
TISp: Timer
When the LIN-bus communication function is used, select the input signal of the p.279 _†
input select
RxD3 pin by setting ISC1 to 1 and TIS07 = 0.
register p
TOEp: Timer For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOE0 to “0”.
p.279 _†
output enable For 78K0R/LG3, be sure to clear bits 15 to 8 of TOE0 to “0”.
p.279 _†
register p
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOE0, bits 15 to 4 of TOE1 to “0”.
p.279 _†
TOp: Timer
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TO0 to “0”.
p.280 _†
output register p For 78K0R/LG3, be sure to clear bits 15 to 8 of TO0 to “0”.
p.280 _†
For 78K0R/LH3, be sure to clear bit 15 to 8 of TO0, bits 15 to 4 of TO1 to “0”.
p.280 _†
TOLp: Timer
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOL0 to “0”.
p.281 _†
output level
For 78K0R/LG3, be sure to clear bits 15 to 8 of TOL0 to “0”.
p.281 _†
register p
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOL0, bits 15 to 4 of TOL1 to “0”.
p.281 _†
TOMp: Timer For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOM0 to “0”.
p.282 _†
output mode
For 78K0R/LG3, be sure to clear bits 15 to 8 of TOM0 to “0”.
p.282 _†
register p
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOM0, bits 15 to 4 of TOM1 to “0”.
p.282 _†
R01UH0004EJ0501 Rev.5.01
967
Jun 20, 2011