UPD78F1502AGK-GAK-AX Datasheet, PDF (473/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(7) Serial flag clear trigger register mn (SIRmn)
SIRmn is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because SIRmn is a trigger register, it is cleared immediately
when the corresponding bit of SSRmn is cleared.
SIRmn can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SIRmn can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears this register to 0000H.
Figure 14-10. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03),
F0148H, F0149H (SIR10), F014AH, F014BH (SIR11),
F014EH, F014FH (SIR13)
After reset: 0000H
Symbol
15 14 13 12 11 10 9
8
7
6
SIRmn
0
0
0
0
0
0
0
0
0
0
R/W
5
4
0
0
3
2
1
0
0 FEC PEC OVC
Tmn Tmn Tmn
FEC
Tmn
Clear trigger of framing error of channel n
0 No trigger operation
1 Clears the FEFmn bit of the SSRmn register to 0.
PEC
Tmn
Clear trigger of parity error flag of channel n
0 No trigger operation
1 Clears the PEFmn bit of the SSRmn register to 0.
OVC
Tmn
Clear trigger of overrun error flag of channel n
0 No trigger operation
1 Clears the OVFmn bit of the SSRmn register to 0.
Caution Be sure to clear bits 15 to 3 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the SIRmn register is read, 0000H is always read.
R01UH0004EJ0501 Rev.5.01
457
Jun 20, 2011