UPD78F1502AGK-GAK-AX Datasheet, PDF (595/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-1. Block Diagram of Serial Interface IICA
SDA0/
P61
WUP
Sub-circuit
for standby
Internal bus
IICA status register (IICS)
IICA control register 0
(IICCTL0)
MSTS ALD EXC COI TRC ACKD STD SPD
IICE LREL WREL SPIE WTIM ACKE STT SPT
Filter
Noise
eliminator
DFC
Slave address
register (SVA)
Match
signal
Clear
Set
IICA shift
register (IICA)
SO latch
DQ
IICWL
Start
condition
generator
Stop
condition
generator
N-ch open-
drain output
PM61
Output
latch
(P61)
Filter
SCL0/
P60
Noise
eliminator
DFC
N-ch open-
drain output
PM60
Output fCLK
latch
(P60)
TRC
Output control
Data hold
time correction
circuit
ACK detector
ACK
generator
Wakeup
controller
Start condition
detector
Stop condition
detector
Serial clock
counter
Serial clock
controller
Counter
Match signal
Serial clock
wait controller
Interrupt request
signal generator
INTIICA
IICS.MSTS, EXC, COI
IICA shift register (IICA)
IICCTL0.STT, SPT
IICS.MSTS, EXC, COI
Bus status
detector
IICA low-level width
setting register (IICWL)
IICA high-level width
WUP CLD
setting register (IICWH)
Internal bus
DAD SMC DFC STCF IICBSY STCEN IICRSV
IICA control register 1
(IICCTL1)
IICA flag register
(IICF)
R01UH0004EJ0501 Rev.5.01
579
Jun 20, 2011