UPD78F1502AGK-GAK-AX Datasheet, PDF (476/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(10) Serial channel stop register m (STm)
STm is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is cleared to 0. Because STmn is a trigger bit, it is cleared immediately when SEmn = 0.
STm can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of STm can be set with an 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears this register to 0000H.
Figure 14-13. Format of Serial Channel Stop Register m (STm)
Address: F0124H, F0125H (ST0), F0164H, F0165H (ST1) After reset: 0000H R/W
Symbol
15 14 13 12 11 10 9
8
7
6
5
STm
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
0 STm STm STm STm
3
2
1
0
STm
n
Operation stop trigger of channel n
0 No trigger operation
1 Clears SEmn to 0 and stops the communication operation.
(Stops with the values of the control register and shift register, and the statuses of the serial clock I/O pin,
serial data output pin, and the FEF, PEF, and OVF error flags retained^Note.)
Note Bits 6 and 5 (TSFmn, BFFmn) of the SSRmn register are cleared.
Caution Be sure to clear bits 15 to 4 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the STm register is read, 0000H is always read.
R01UH0004EJ0501 Rev.5.01
460
Jun 20, 2011