UPD78F1502AGK-GAK-AX Datasheet, PDF (810/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 22 RESET FUNCTION
Timer array units 0, 1
(TAU0, TAU1)
Real-time counter
Clock output/buzzer
output controller
Watchdog timer
A/D converter
D/A converter
Operational amplifier
Voltage reference
Table 22-2. Hardware Statuses After Reset Acknowledgment (2/4)
Hardware
Timer channel stop trigger registers 0, 1 (TT0, TT1)
Timer clock select registers 0, 1 (TPS0, TPS1)
Timer channel output registers 0, 1 (TO0, TO1)
Timer channel output enable registers 0, 1 (TOE0, TOE1)
Timer channel output level registers 0, 1 (TOL0, TOL1)
Timer channel output mode registers 0, 1 (TOM0, TOM1)
Sub-count register (RSUBC)
Second count register (SEC)
Minute count register (MIN)
Hour count register (HOUR)
Week count register (WEEK)
Day count register (DAY)
Month count register (MONTH)
Year count register (YEAR)
Watch error correction register (SUBCUD)
Alarm minute register (ALARMWM)
Alarm hour register (ALARMWH)
Alarm week register (ALARMWW)
Real-time counter control register 0 (RTCC0)
Real-time counter control register 1 (RTCC1)
Real-time counter control register 2 (RTCC2)
Clock output select registers 0, 1 (CKS0, CKS1)
Status After Reset
Acknowledgment^{Note 1}
0000H
0000H
0000H
0000H
0000H
0000H
0000H
00H
00H
12H
00H
01H
01H
00H
00H
00H
12H
00H
00H
00H
00H
00H
Enable register (WDTE)
10-bit A/D conversion result register (ADCR)
8-bit A/D conversion result register (ADCRH)
A/D converter mode register (ADM)
A/D converter mode register 1 (ADM1)
Analog reference voltage control register (ADVRC)
Analog input channel specification register (ADS)
A/D port configuration register (ADPC)
D/A conversion value setting registers W0, W1 (DACSW0, DACSW1)
8-bit D/A conversion value setting registers 0, 1 (DACS0, DACS1)
D/A converter mode register (DAM)
Operational amplifier control register (OAC)
Analog reference voltage control register (ADVRC)
1AH/9AH^{Note 2}
0000H
00H
00H
00H
00H
00H
10H
0000H
00H
00H
00H
00H
Notes 1.
2.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
The reset value of WDTE is determined by the option byte setting.
Remark The SFR and 2nd SFR mounted depend on the product. Refer to 3.2.4 Special function registers (SFRs)
and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
R01UH0004EJ0501 Rev.5.01
794
Jun 20, 2011