UPD78F1502AGK-GAK-AX Datasheet, PDF (665/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-32. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4)
(2) Address ~ data ~ data
Master side
IICA
ACKD
(ACK detection)
WTIM
H
(8 or 9 clock wait)
ACKE
(ACK control) ^H
MSTS
(communication status) ^H
STT
(ST trigger)
L
SPT
(SP trigger)
L
WREL
(wait cancellation) ^L
INTIICA
(interrupt)
TRC
(transmit/receive) ^H
Note 1
<5>
Note 1
<9>
Bus line
SCL0 (bus)
(clock line)
<4>
<8>
SDA0 (bus)
(data line)
W ACK
D17 _{D16 D15 D14 D13 D12 D11 D10} ACK
D27
<3>
<7>
Slave side
IICA
ACKD
(ACK detection)
STD
(ST detection)
SPD
(SP detection) ^L
WTIM
H
(8 or 9 clock wait)
ACKE
(ACK control) ^H
MSTS
(communication status) ^L
WREL
(wait cancellation)
INTIICA
(interrupt)
TRC
(transmit/receive) ^L
<6> Note 2
<10> _{Note 2}
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
2. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
R01UH0004EJ0501 Rev.5.01
649
Jun 20, 2011