UPD78F1502AGK-GAK-AX Datasheet, PDF (574/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
14.7.2 Data transmission
Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field.
After all data are transmitted to the slave, a stop condition is generated and the bus is released.
Simplified I²C
IIC10
IIC20
Target channel
Pins used
Channel 2 of SAU0
SCL10, SDA10 ^Note
Channel 0 of SAU1
SCL20, SDA20 ^Note
Interrupt
INTIIC10
INTIIC20
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Parity error detection flag (PEFmn)
Transfer data length 8 bits
Transfer rate
Max. fCLK/4 [MHz] (SDRmn [15:9] = 1 or more)
fCLK: System clock frequency
However, the following condition must be satisfied in each mode of I²C.
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Data level
Forward output (default: high level)
Parity bit
No parity bit
Stop bit
Appending 1 bit (for ACK reception timing)
Data direction
MSB first
Note To perform communication via simplified I²C, set the data I/O pins (SDA10, SDA20) in the N-ch open-drain output
(VDD tolerance) mode (POM14 = 1, POM11 = 1) by using the port output mode register 1 (POM1) (see 4.3
Registers Controlling Port Function for details). When communicating with an external device with a different
potential, set the N-ch open-drain output (VDD tolerance) mode (POM15 = 1, POM10 = 1) also for the clock
input/output pins (SCL10, SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V)
for details).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
R01UH0004EJ0501 Rev.5.01
558
Jun 20, 2011