UPD78F1502AGK-GAK-AX Datasheet, PDF (742/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
Figure 18-7. Example of Setting for CSI Consecutive Transmission
Start
DEN0 = 1
DSA0 = 44H
DRA0 = FB00H
DBC0 = 0100H
DMC0 = 48H
Setting for CSI transfer
DST0 = 1
STG0 = 1
DMA is started.
INTCSI10 occurs.
User program
processing
DMA0 transfer
CSI
transmission
Occurrence of
INTDMA0
DST0 = 0^Note
DEN0 = 0
RETI
End
Hardware operation
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA0 (INTDMA0), set DST0 to 0 and then DEN0 to 0 (for details, refer to 18.5.7
Forced termination by software).
The fist trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it start by a software
trigger.
CSI transmission of the second time and onward is automatically executed.
A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011