UPD78F1502AGK-GAK-AX Datasheet, PDF (637/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Figure 15-29. Master Operation in Multi-Master System (3/3)
C
Writing IICA
Starts communication
(specifies an address and transfer direction).
INTIICA
interrupt occurs?
Yes
MSTS = 1?
Yes
No
ACKD = 1?
Yes
TRC = 1?
Yes
WTIM = 1
No
Waits for detection of ACK.
No
2
No
Writing IICA
Starts transmission.
INTIICA
interrupt occurs?
Yes
MSTS = 1?
No
Waits for data transmission.
No
Yes
2
ACKD = 1?
No
Yes
No
Transfer end?
Yes
Restart?
No
Yes
SPT = 1
STT = 1
END
C
ACKE = 1
WTIM = 0
WREL = 1
Starts reception.
INTIICA
interrupt occurs?
Yes
MSTS = 1?
Yes
Reading IICA
No
Waits for data reception.
No
2
Transfer end?
No
Yes
WTIM = WREL = 1
ACKE = 0
INTIICA
interrupt occurs?
Yes
MSTS = 1?
Yes
No
Waits for detection of ACK.
No
2
2
EXC = 1 or COI = 1? ^No
Yes
Slave operation
1
Does not participate
in communication.
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
2. To use the device as a master in a multi-master system, read the MSTS bit each time interrupt INTIICA
has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICS and IICF
registers each time interrupt INTIICA has occurred, and determine the processing to be performed next.
R01UH0004EJ0501 Rev.5.01
621
Jun 20, 2011