UPD78F1502AGK-GAK-AX Datasheet, PDF (261/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (5/6)
(11) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (C) (X1 clock: 2 MHz ≤
fX ≤ 10 MHz)
(D) → (C) (X1 clock: 10 MHz
< fX ≤ 20 MHz)
(D) → (C) (external main
clock)
OSTS
Register
Note 1
Note 1
Note 1
CSC Register
MSTOP
0
0
0
OSMC
Register
FSEL
0
1 ^{Note 2}
0/1
OSTC
Register
Must be
checked
Must be
checked
Must not be
checked
CKC Register
MCM0
1
1
1
CSS
0
0
0
Unnecessary if the CPU is operating with
the high-speed system clock
Unnecessary
if these
registers are
already set
Notes 1. Set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
2. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
(12) CPU clock changing from 20 MHz internal high-speed oscillation clock (J) to internal high-speed oscillation
clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(J) → (B)
SELDSC
0
DSCCTL Register
DSCON
0
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
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Jun 20, 2011