UPD78F1502AGK-GAK-AX Datasheet, PDF (549/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
14.6.2 UART reception
UART reception is an operation wherein the 78K0R/Lx3 microcontrollers asynchronously receive data from another
device (start-stop synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both
the odd- and even-numbered channels must be set.
UART
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
UART0
UART1
UART2
UART3
Channel 1 of SAU0
Channel 3 of SAU0
Channel 1 of SAU1
Channel 3 of SAU1
RxD0
RxD1
RxD2
RxD3
INTSR0
INTSR1
INTSR2
INTSR3
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
INTSRE0
INTSRE1
INTSRE2
INTSRE3
• Framing error detection flag (FEFmn)
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
5, 7 or 8 bits
Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 2¹¹ × 128) [bps] ^Note
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
Appending 1 bit
MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
fCLK: System clock frequency
2. For 78K0R/LF3, UART0 is not mounted.
R01UH0004EJ0501 Rev.5.01
533
Jun 20, 2011