UPD78F1502AGK-GAK-AX Datasheet, PDF (237/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
(8) Operation speed mode control register (OSMC)
This register is used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates at a low speed with a system clock of 10 MHz or less, the power consumption can be
lowered by setting this register to the default value, 00H.
OSMC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-9. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
OSMC RTCLPC
0
0
0
0
0
FLPC
FSEL
RTCLPC
0
1
Setting in subsystem clock HALT mode
Enables subsystem clock supply to peripheral functions.
(See Table 21-1 Operating Statuses in HALT Mode (2/3) for the peripheral functions whose
operations are enabled.)
Stops subsystem clock supply to peripheral functions except real-time counter, clock
output/buzzer output, and LCD controller/driver.
FLPC
0
0
1
1
FSEL
0
1
0
1
fCLK frequency selection
Operates at a frequency of 10 MHz or less (default).
Operates at a frequency higher than 10 MHz.
Operates at a frequency of 1 MHz.
Setting prohibited
Cautions 1. Write “1” to FSEL before the following two operations.
• Changing the clock prior to dividing fCLK to a clock other than fIH.
• Operating the DMA controller.
2. The CPU waits (140.5 clock (fCLK)) when “1” is written to the FSEL bit.
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of fX can continue even while the
CPU is waiting.
3. To increase fCLK to 10 MHz or higher, set FSEL to “1”, then change fCLK after two or
more clocks have elapsed.
4. Confirm that the clock is operating at 10 MHz or less before setting FSEL = 0.
5. To shift to STOP mode while VDD ≤ 2.7 V, set FSEL = 0 after setting fCLK to 10 MHz or
less.
6. The HALT mode current when operating on the subsystem clock can be reduced by
setting RTCLPC to 1. However, the clock cannot be supplied to peripheral functions
except the real-time counter in the subsystem clock HALT mode. Set bit 7 (RTCEN)
of PER0 to 1 and bits 0 to 6 of PER0 to 0 before setting the subsystem clock HALT
mode.
7. Once FLPC has been set from 0 to 1, setting it back to 0 from 1 other than by reset is
prohibited.
8. When setting FSEL to “1”, do so while RMC = 00H.
When setting FLPC to “1”, do so while RMC = 5AH.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011