UPD78F1502AGK-GAK-AX Datasheet, PDF (510/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(4) Processing flow (in continuous transmission/reception mode)
Figure 14-44. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
SOp pin
INTCSIp
MDmn0
TSFmn
Transmit data 1 Transmit data 2 Receive data 1 Transmit data 3
Write
Write
Write
Read
Receive data 3
Receive data 2
Read
Read
Receive data 1
Reception & shift operation
Transmit data 1
Receive data 2
Reception & shift operation
Transmit data 2
Receive data 3
Reception & shift operation
Transmit data 3
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
BFFmn
<1> <2><3>
(Note 1)
<2> _{(Note 2)} <3>
<4> <2>
<3> <4> <5>
(Note 2)
<6><7> <8>
Notes 1. When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 14-45 Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
R01UH0004EJ0501 Rev.5.01
494
Jun 20, 2011