UPD78F1502AGK-GAK-AX Datasheet, PDF (305/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
6.4 Channel Output (TOpq pin) Control
6.4.1 TOpq pin output circuit configuration
Interrupt signal of the master channel
(INTTMpq)
Interrupt signal of the slave channel
(INTTMpr)
Figure 6-26. Output Circuit Configuration
<5>
TOp register
<1>
<2>
<3>
TOLpq
TOMpq
Set
Reset/toggle
<4>
TOpq pin
Internal bus
TOEpq
TOpq write signal
The following describes the TOpq pin output circuit.
<1> When TOMpq = 0 (toggle mode), the set value of the TOLp register is ignored and only INTTMpr (slave
channel timer interrupt) is transmitted to the TOp register.
<2> When TOMpq = 1 (combination operation mode), both INTTMpq (master channel timer interrupt) and
INTTMpr (slave channel timer interrupt) are transmitted to the TOp register.
At this time, the TOLp register becomes valid and the signals are controlled as follows:
When TOLpq = 0: Forward operation (INTTMpq → set, INTTMpr → reset)
When TOLpq = 1: Reverse operation (INTTMpq → reset, INTTMpr → set)
When INTTMpq and INTTMpr are simultaneously generated, (0% output of PWM), INTTMpr (reset signal)
takes priority, and INTTMpq (set signal) is masked.
<3> When TOEpq = 1, INTTMpq (master channel timer interrupt) and INTTMpr (slave channel timer interrupt) are
transmitted to the TOpq register. Writing to the TOp register (TOpq write signal) becomes invalid.
When TOEpq = 1, the TOpq pin output never changes with signals other than interrupt signals.
To initialize the TOpq pin output level, it is necessary to set TOEpq = 0 and to write a value to TOpq.
<4> When TOEpq = 0, writing to TOpq bit to the target channel (TOpq signal) becomes valid. When TOEpq = 0,
neither INTTMpq (master channel timer interrupt) nor INTTMpr (slave channel timer interrupt) is transmitted
to TOpq register.
<5> The TOp register can always be read, and the TOpq pin output level can be checked.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011