UPD78F1502AGK-GAK-AX Datasheet, PDF (594/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
CHAPTER 15 SERIAL INTERFACE IICA
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Item
Serial interface
IICA
78K0R/LF3
80 pins
−
78K0R/LG3
100 pins
1 ch
78K0R/LH3
128 pins
15.1 Functions of Serial Interface IICA
Serial interface IICA has the following three modes.
(1) Operation stop mode
This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
(2) I²C bus mode (multimaster supported)
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a serial
data bus (SDA0) line.
This mode complies with the I²C bus format and the master device can generated “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus. The
slave device automatically detects these received status and data by hardware. This function can simplify the part
of application program that controls the I²C bus.
Since the SCL0 and SDA0 pins are used for open drain outputs, IICA requires pull-up resistors for the serial clock
line and the serial data bus line.
(3) Wakeup mode
The STOP mode can be released by generating an interrupt request signal (INTIICA) when an extension code from
the master device or a local address has been received while in STOP mode. This can be set by using the WUP bit
of IICA control register 1 (IICCTL1).
Figure 15-1 shows a block diagram of serial interface IICA.
R01UH0004EJ0501 Rev.5.01
578
Jun 20, 2011