UPD78F1502AGK-GAK-AX Datasheet, PDF (991/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(19/39)
Page
A/D
converter
Input impedance This A/D converter charges a sampling capacitor for sampling during sampling time. p.415 _†
of ANI0 to
Therefore, only a leakage current flows when sampling is not in progress, and a
ANI10, ANI15 current that charges the capacitor flows during sampling. Consequently, the input
pins
impedance fluctuates depending on whether sampling is in progress, and on the
other states.
To make sure that sampling is effective, however, it is recommended to keep the
output impedance of the analog input source to within 1 kΩ, and to connect a
capacitor of about 100 pF to the ANI0 to ANI10 and ANI15 pins (see Figure 10-28).
AVREFP pin input A series resistor string of several tens of kΩ is connected between the AVREFP and p.416 _†
impedance
AVREFM (or AVSS) pins.
Therefore, if the output impedance of the reference voltage supply is high, this will
result in a series connection to the series resistor string between the AVREFP and
AVREFM (or AVSS) pins, resulting in a large reference voltage (AVREF) error of A/D
converter.
Interrupt request The interrupt request flag (ADIF) is not cleared even if the analog input channel p.416 _†
flag (ADIF)
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just before
the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read
immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the
post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D
conversion operation is resumed.
Conversion
The first A/D conversion value immediately after A/D conversion starts may not fall p.416 _†
results just after within the rating range if the ADCS bit is set to 1 within 1 μs after the ADCE bit was
A/D conversion set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as
start
polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
A/D conversion When a write operation is performed to A/D converter mode register (ADM), A/D _{p.417 †}
result register converter mode register 1 (ADM1), analog input channel specification register (ADS),
(ADCR,
and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may
ADCRH) read become undefined. Read the conversion result following conversion completion
operation
before writing to ADM, ADM1, ADS, or ADPC. Using a timing other than the above
may cause an incorrect conversion result to be read.
Internal
The equivalent circuit of the analog input block is shown below. (See Figure 10-30.) p.417 _†
equivalent circuit
Rewriting
Rewriting DACSWn (n = 0, 1) during A/D conversion is prohibited when both the _{p.417 †}
DACSWn during positive reference voltage of A/D converter (ADREFP) and the positive reference
A/D conversion voltage of the D/A converter (DAREF) are the voltage reference output (VREFOUT)
(VRSEL = 1 and DAREF = 1). Rewrite it when conversion operation is stopped
(ADCS = 0).
R01UH0004EJ0501 Rev.5.01
975
Jun 20, 2011